A gate driver circuit applied to a display device includes multiple levels of shift register units. Each shift register unit includes a pull-up node control unit, a pull-down node control unit and a gate driving signal output unit. The pull-up node control unit is connected to a pull-up node and configured to control a potential at the pull-up node. The pull-down node control unit is connected to a pull-down node and configured to control a potential at the pull-down node. The gate driving signal output unit is configured to control the output of a gate driving signal in accordance with the potential at the pull-up node and the potential at the pull-down node. The gate driving signal serves as a carry signal for an adjacent level shift register unit, and thus its response speed is relatively small. In addition, a relatively large drift may occur for a thin film transistor (TFT) as a main element of the shift register unit in the case that a direct current (DC) is applied to the TFT for a long time period or in the case that the TFT operates at a high temperature, so its reliability may be reduced. Further, in the case that the TFT is a polycrystalline silicon TFT, a relatively large leakage current may occur in the case that the TFT is turned off, so the power consumption may increase and even a normal operation of the shift register unit may be adversely affected.